2020.12-2022.12   2138cc太阳集团电子科学与工程学院/微电子学院，讲师

2023.1-2024.12     2138cn太阳集团古天乐，讲师

2025.1-至今          2138cn太阳集团古天乐，副教授、青年首席教授

本科生课程：计算机科学基础II

研究生课程：超大规模集成电路设计自动化导论

标准单元版图自动生成（晶体管级布局布线）；模拟电路自动布局布线；PCB自动布局布线；人工智能辅助的数字电路布局布线；3D布局。

主持国家重点研发计划青年科学家项目，国家自然科学基金青年项目，江苏省自然科学基金青年项目，与国内头部设计企业和EDA企业持续合作研究。

Publications (* denotes corresponding author.)

2025:

1.        Keyu Peng, Yinuo Wu, Zhengzhe Zheng, Hao Gu, Ziran Zhu*, Chao Wang, Jun Yang, DiSPlace: Diffusion-Sharing-Driven Transistor-Level Placement Beyond Standard-Cell Boundaries for DTCO, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Oct. 26–30, 2025.

2.        Zhengzhe Zheng, Keyu Peng, Yinuo Wu, Hao Gu, Chao Wang, Ziran Zhu*, Standard Cell Layout Generator Empowered by ILP-based Routing with Dynamic Grid-Shifting for Advanced Nodes, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Oct. 26–30, 2025.

3.        Zhengzhe Zheng, Yinuo Wu, Keyu Peng, Chao Wang*, Ziran Zhu*, Comprehensive Placement and Routing Framework with Guaranteed In-Cell Routability for Synthesizing Complementary-FET Cells, 62th ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025.

4.        Xinglin Zheng, Hao Gu, Keyu Peng, Youwen Wang, Wenxing Zhu, Ziran Zhu*, Late Breaking Results: Customized Diffusion Model Empowered by Heterogeneous Graph Network for Effective Floorplanning, 62th ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025.

5.        Yilin Li, Wei Fu, Hao Gu, Ziran Zhu*, HDPlacer: A Hierarchy and Dataflow-Aware Macro Placer for Modern SoCs, International Symposium of EDA (ISEDA), May 9–12, 2025.

6.        Yichen Lu, Fuxing Huang, Ziran Zhu*, An Effective Fixed-Outline Floorplanning Algorithm for Rectilinear Soft Modules, International Symposium of EDA (ISEDA), May 9–12, 2025.

7.        Hao Gu, Xinglin Zheng, Youwen Wang, Keyu Peng, Ziran Zhu*, Jun Yang, Multiscale Feature Attention and Transformer Based Congestion Prediction for Routability-Driven FPGA Macro Placement, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Lyon, France, Mar. 31–Apr. 02, 2025.

8.        Hao Gu, Jian Gu, Keyu Peng, Jianli Chen, Jun Yang, Ziran Zhu*, Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol., no. , pp. , 2025. (Early Access:https://ieeexplore.ieee.org/abstract/document/10972071/)

9.        Hao Gu, Youwen Wang, Xinglin Zheng, Keyu Peng, Ziran Zhu*, Jianli Chen, Jun Yang, Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 44, no. 6, pp. 2378-2391, 2025.

10.     Disi Lin, Chuandong Chen*, Rongshan Wei, Qinghai Liu, Huan He, Ziran Zhu, Zhifeng Lin, Jianli Chen, Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB, Integration, the VLSI Journal, vol. 100, pp. 1-11, 2025.

2024:

11.     Xiqiong Bai*, Yilu Chen, Zhifeng Lin, Min Wei, Zhijie Cai, Ziran Zhu, Jianli Chen, A fast and high-performance global router with enhanced congestion control, Integration, the VLSI Journal, vol. 100, pp. 1-11, 2024.

12.     Ziran Zhu*, Yilin Li, Miaodi Su, Shu Zhang, Haiyuan Su, Yifeng Xiao, Huan He, Jianli Chen, Yao-Wen Chang, Subgraph matching-based reference placement for printed circuit board designs, The Journal of Supercomputing, Volume 80, pages 24324–24357, 2024. 

13.     Hong Liu, Xiqiong Bai, Ziran Zhu*, Effective Legalization with Cell Version Replacement for Hybrid-Row-Height Circuit Designs, International Symposium of EDA (ISEDA), May 10–13, 2024.

14.     Chuandong Chen, Haiming Lin, Miaodi Su, Huan He, Jianli Chen, Ziran Zhu*, Subgraph Matching with Diversity Handling and Its Applications to PCB Placement, International Symposium of EDA (ISEDA), May 10–13, 2024.

15.     Hao Gu, Jian Gu, Keyu Peng, Jun Yang, Ziran Zhu*, Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints, 61th ACM/IEEE Design Automation Conference(DAC), San Francisco, Jun. 23–27, 2024.

16.     Biao Liu, Congyu Qiao, Ning Xu*, Xin Geng*, Ziran Zhu, Jun Yang, “Variational Label-Correlation Enhancement for Congestion Prediction”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), South Korea, Jan. 22–25, 2024.

17.     Zijun Li, Ziran Zhu*, Huan He, and Jianli Chen, An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs, Integration, the VLSI Journal, vol. 94, pp. 1-9, January 2024. 

18.     Hao Gu, Jian Gu, Keyu Peng, Ziran Zhu*, Ning Xu, Xin Geng, and Jun Yang, LAMPlace: Legalization-Aided Reinforcement Learning Based Macro Placement for Mixed-Size Designs With Preplaced Blocks, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 71, no. 8, pp. 3770-3774, August 2024.

19.     Ziran Zhu, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang, and Yao-Wen Chang*, High-performance Placement Engine for Modern Large-scale FPGAs with Heterogeneity and Clock Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 3, pp. 956-969, March 2024. 

20.     Ziran Zhu*, Yuejian Shi, Yangjie Mei, Fuheng Shen, Hong Liu, and Jun Yang, High-Performance 3-D Placement Engine With Physical-Aware Incremental Partitioning, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 71, no. 3, pp. 1151-1155, March 2024. 

21.     Ziran Zhu*, Fuheng Shen, Yangjie Mei, Jianli Chen, Jun Yang, An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting, IEEE Transactions on Circuits and Systems II: Express Briefs(TCAS-II), vol. 71, no. 1, pp. 161-165, January 2024.

2023：

22.     朱自然*，张勋*，陆亦辰，彭柯宇；超大规模集成电路宏模块布局研究进展，中国基础科学，2023.

23.     Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang*, Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints, 60th ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 09–13, 2023.

24.     Jian Gu, Hao Gu, Ke Liu, Ziran Zhu*, An Effective Macro Placement Algorithm Based On Curiosity-Driven Reinforcement Learning, 2023 International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, May 08-11, 2023.

25.     Chuandong Chen, Dishi Lin, Rongshan Wei, Qinghai Liu, Ziran Zhu*, Jianli Chen, Efficient Global Optimization for Large Scaled Ordered Escape Routing, 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo Japan, January 16-19, 2023.

26.     Ke Liu, Jian Gu, Hao Gu, Ziran Zhu*, A Hybrid Reinforcement Learning and Genetic Algorithm for VLSI Floorplanning, 15th International Conference on Machine Learning and Computing (ICMLC), Zhuhai, China, February 17-20, 2023.

2022：

27.     Ziran Zhu*, Fuheng Shen, Yangjie Mei, Zhipeng Huang, Jianli Chen, and Jun Yang, A Robust Global Routing Engine with High-accuracy Cell Movement under Advanced Constraints, 41th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, Oct. 30–Nov. 3, 2022.

28.     Ziran Zhu*, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, and Yao-Wen Chang*, High-performance Placement for Large-scale Heterogeneous FPGAs with Clock Constraints, 59th ACM/IEEE Design Automation Conference(DAC), San Francisco, Jul. 10–14, 2022.

29.     Zijun Li, Yangjie Mei, Jingwen Lin, and Ziran Zhu*, An Effective Routability-Driven Packing Algorithm for Large-Scale Heterogeneous FPGAs, IEEE 4th International Conference on Circuits and Systems (ICCS), Chengdu, China, September 23-26, 2022.

30.     Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu*, Jianli Chen, and Yao-Wen Chang, Late Breaking Results: Subgraph Matching Based Reference Placement for PCB Designs, 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 10–14, 2022.

31.     Xiqiong Bai*, Ziran Zhu, Peng Zou, Jianli Chen*, Jun Yu, and Yao-Wen Chang, Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification, 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Virtual Conference, Jan. 17-20, 2022.

32.     Zhipeng Huang, Haishan Huang, Runming Shi, Xu Li, Xuan Zhang, Weijie Chen, Jiaxiang Wang, and Ziran Zhu*, Detailed Placement and Global Routing Co-Optimization with Complex Constraints, Electronics, vol. 11, no. 1, pp.51:1-51:22, 2022.

33.     Jianli Chen, Ziran Zhu, Longkun Guo, Yu-Wei Tseng, and Yao-Wen Chang*, Mixed-Cell-Height Placement with Drain-to-Drain Abutment and Region Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 4, pp.1103-1115, April 2022.

34.     Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen, Tingshen Lan, Xingquan Li, Jun Yu, Wenxing Zhu, and Yao-Wen Chang*, Timing-Aware Fill Insertions with Design-Rule and Density Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 10, pp.3529-3542, October 2022.

35.     Jianli Chen , Zhipeng Huang, Ziran Zhu, Zheng Peng, Wenxing Zhu , and Yao-Wen Chang*, Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 12, pp.5541-5553, December 2022.

2021：

36.     Xiqiong Bai*, Ziran Zhu, Peng Zou, Lichong Sun, and Jianli Chen*, Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification, 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, Dec. 5-9, 2021.

37.     Zhipeng Huang*, Haokai Sun, Huimin Wang, Ziran Zhu, Jun Yu, and Jianli Chen*, Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints, 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, Dec. 5-9, 2021.

38.     Ziran Zhu, Zhipeng Huang, Jianli Chen, and Longkun Guo*, Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles, Complexity, 2021. 

2020：

39.     Ziran Zhu, Jianli Chen, Wenxing Zhu, and Yao-Wen Chang*, Mixed-Cell-Height Legalization Considering Technology and Region Constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 12, pp. 5128-5141, December 2020.

40.     Jianli Chen, Ziran Zhu, Wenxing Zhu, and Yao-Wen Chang*, A Robust Modulus-based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 26, no. 2, pp. 15:1-15:28, December 2020.

41.     Jianli Chen*, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, and Yao-Wen Chang*, Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation, 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 19-23, 2020.

42.     Ziran Zhu, Zhipeng Huang, Peng Yang, Wenxing Zhu, Jianli Chen*, Hanbin Zhou, and Senhua Dong, Mixed-Cell-Height Legalization Considering Complex Minimum Width Constraints and Half-Row Fragmentation Effect, Integration, the VLSI Journal, vol. 71, pp. 1-10, March 2020.

43.     Zhipeng Huang, Zhifeng Lin, Ziran Zhu, and Jianli Chen*, An Improved Simulated Annealing Algorithm with Excessive Length Penalty for Fixed-Outline Floorplanning, IEEE Access, vol. 8, pp. 50911-50920, March 2020.

2019：

44.     Zhonghua Zhou*, Ziran Zhu, Jianli Chen, Yuzhe Ma, Bei Yu, Tsung-Yi Ho, Guy Lemieux, and Andre Ivanov, Congestion-aware Global Routing using Deep Convolutional Generative Adversarial Networks, ACM/IEEE Workshop on Machine Learning for CAD, Alberta, Canada, Sept. 3-4, 2019.

2018：

45.     Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, and Yao-Wen Chang*, Generalized Augmented Lagrangian and its Applications to VLSI Global Placement, 55th ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 24-28, 2018.

46.     Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, and Yao-Wen Chang*, Mixed-Cell-Height Legalization Considering Technology and Region Constraints, 37th ACM/IEEE International Conference on Computer-Aided Design (ICCAD), San Diego, Nov. 5-8, 2018.

2017：

47.     Xingquan Li, Ziran Zhu, and Wenxing Zhu*, Discrete Relaxation Method for Triple Patterning Lithography Layout Decomposition, IEEE Transactions on Computers (TC), vol. 66, no. 2, pp. 285-298, February 2017.

48.     Jianli Chen, Ziran Zhu, Wenxing Zhu, and Yao-Wen Chang*, Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs, 54th ACM/IEEE Design Automation Conference (DAC), Austin, Jun. 18-22, 2017. (Best Paper Award)

49.     Jianli Chen, Yan Liu, Ziran Zhu, and Wenxing Zhu*, An Adaptive Hybrid Memetic Algorithm for Thermal-aware Non-slicing VLSI Floorplanning, Integration, the VLSI Journal, vol. 58, pp. 245-252, June 2017.